Lab 3 Specifications

Lab 3 represents the culmination of our practice with Verilog design. The specifications reflect that: the Verilog style and structure is relaxed to allow you to make more design choices, and the block diagram specs are in full force so that you effectively document your Verilog design. The specs are also strict about finite state machine format because that is a key learning goal in class.

Hardware Specifications

Proficiency

• Circuit correctly reads inputs from \(4 \times 4\) keypad when one digit is touched at a time.
• Dual seven-segment display shows the last two hexadecimal digits pressed.
• Each button press registered only once.

Excellence

• Design only registers first button press if additional buttons are pressed down while holding down one button.
• If multiple buttons are held down, display updates to a new value when all but one button is released. (i.e., design registers the last held button as a valid single key press when leaving a multi-press condition.)
• Design does not lock up or otherwise misfire when multiple buttons are pressed at once. (i.e., it just holds the current values on the display, never displays a weird intermediate digit, and functions properly again when the buttons are released.)

Verilog Structure and Style Specifications

Proficiency

• Logic elements with state (like counters, synchronizers or finite state machines) are wrapped in appropriate modules.
• Counters are reused from previous designs. (Minor adjustments, especially to respond to instructor feedback, are allowed. But any changes to the Verilog need to be verified by re-running the testbench.)
• Seven segment and multiplexing logic are reused from previous designs. (Minor adjustments, especially to respond to instructor feedback, are allowed. But any changes to the Verilog need to be verified by re-running the testbench.)
• Top level module consists only of instantiated modules and trivial logic; don’t introduce new state to verify at the top!
• A debouncing strategy is implemented, you can’t just count on a lucky keypad!
• Asynchronous inputs are synchronized.
• Style conventions from previous labs (module names, descriptive variables, etc.) are still followed. See HDL specs

Excellence

• Finite state machines are all implemented in an appropriate form that we discussed in lecture: canonical, non-canonical (e.g.: instantiated counter + output logic), or communicating. Be especially careful to avoid embedding one state machine inside another (e.g.: counter embedded inside of canonical form instead of building communicating modules.)
• Design is fully synchronous, strobing enables as appropriate to manage multiple clock rates.

Simulation Specifications

Proficiency

• All modules, including top, are covered by an automatic testbench that fully exercises combinational behavior (for combinational modules), key state transitions (for sequential modules), or interconnections and otherwise untestable logic and signals (for the top).
• All simulations of new modules are captured as legible waveform screenshots in report. Previously verified modules don’t need to be shown again, though do provide links to previous labs in case we need to check something.

Excellence

• Keypad stimulus implemented: column assertions are of appropriate polarity, arrive at different asynchronous positions relative to the system clock (including right on top of it), and include switch bounce.

Other Documentation

Proficiency

• Report includes state transition diagram(s) illustrating the operation of the system.
• Report includes state transition table to document the nextstate and output values for each state based on the current state and inputs.
• Report includes synthesizer output files showing that design has no latches and no tristate buffers.

Excellence

• State transition diagram and table are completely specified and error free (i.e., all transitions between states are specified, output conditions specified in each state)
• Report explains your switch debouncing strategy and discusses the tradeoffs between your chosen method and others.
• Report explains your FSM partitioning, including decisions about what FSMs communicate, and discusses tradeoffs between your chosen method and others.

Schematic Specifications

Proficiency

• Schematic correctly represents the circuit that was built on the breadboard.
• No parts of motherboard schematic replicated. Shows only off-board components. Indicate on-board components with a brief paragraph that links the motherboard schematic (here).
• No parts internal to the chip (e.g., internal pullup resistors) drawn on schematic. Indicate important pullups, capacitors, etc. with comments instead.
• All pin names labeled.
• All pin numbers labeled.
• Crossing wires clearly identified as junction or unconnected.
• Neat layout (e.g., clear organization and spacing).
• All parts labeled with part number.
• All component values present.

Excellence

• Standard symbols used for all components where applicable.
• Signals “flow” from left to right where possible (e.g., inputs on left hand side, outputs on right hand side, power on top, ground on bottom)
• Title block with author name, title, and date.

Block Diagram Specifications

Proficiency

• Each module is represented by a block diagram
• Bare logic in all module is represented by appropriately drawn gates.
• Submodules in each module are represented by blocks inside of the instantiating module.
• Submodules have all ports represented by pin symbols on the boundary of the submodule, each with a port name.
• Submodules indicate the name of the module being instantiated and the name of the instance.
• All connections between module ports, logic and submodules are indicated.
• Module ports are represented by pin symbols on the boundary of the module and labeled with port names
• All nets internal to the module are labeled, even when they share a name with a port on a module/submodule boundary.

Excellence

• Appropriate use of bus notation for multi-bit signals (e.g., data[7:0] for an 8-bit bus), including fan-in and fan-out when needed.
• Appropriate use of implicit connections (i.e.: connect-by-label-name) to reduce routing connection
• Block diagram is an exact, 1:1 representation of the Verilog code.

Lab Writeup

Proficiency and Excellence

• Documentation embedded in a well-structured, concise report with one section per major deliverable. Sections should match structure of other specs.
• Spoiler tags are used to hide screenshots and code. Some unspoilered entries (~1 waveform, essential code snippets) allowed if they are essential to the narrative, kept to a minimum.
• Writeup contains minimal spelling or grammar issues and any errors do not significantly detract from clarity of the writeup.
• Statement of whether the design meets all the requirements. If not, list the shortcomings.
• AI prototype attempted and some reflection is recorded.
• Number of hours spent working on the lab are included.
• (Optional) List comments or suggestions on what was particularly good about the assignment or what you think needs to change in future versions.